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Vias for high-speed PCB circuit board design

source:Industry News release time:2022-08-18 Article author:yu Popular:pcb

  Vias for high-speed PCB circuit board design(图1)

  At present, the design of high-speed pcb circuit boards is widely used in communications, computers, graphics and image processing and other fields. All high-tech value-added electronic product designs are pursuing low power consumption, low electromagnetic radiation, high reliability, miniaturization, light weight, etc. Features, in order to achieve the above goals, the via design is an important factor in high-speed pcb design. It consists of the hole, the pad area around the hole and the POWER layer isolation area, and is usually divided into three categories: blind vias, buried vias and through vias. In the process of pcb circuit board design, through the analysis of the parasitic capacitance and parasitic inductance of the via hole, some precautions in the design of high-speed pcb via hole are summarized.

  1. Via

  Vias are an important factor in the design of multi-layer pcb circuit boards. A via is mainly composed of three parts, one is the hole; the other is the pad area around the hole; the third is the POWER layer isolation area. The process of the via hole is to coat a layer of metal on the cylindrical surface of the hole wall of the via hole by chemical deposition to connect the copper foils that need to be connected in the middle layers, and the upper and lower sides of the via hole are made into ordinary pads. The shape can be directly connected with the lines on the upper and lower sides, or not connected. Vias can be used to electrically connect, fix or position devices. The schematic diagram of the via hole is shown in Figure 1.

  Vias are generally divided into three categories: blind vias, buried vias and through vias.

  Blind hole: refers to the surface of the top and bottom layers of the printed circuit board, with a certain depth, used for the connection of the surface circuit and the underlying inner circuit, the depth of the hole and the diameter of the hole usually do not exceed a certain ratio.

  Buried hole: refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board.

  Both blind vias and buried vias are located in the inner layer of the circuit board, and are completed by the through-hole forming process before lamination. During the formation of the vias, several inner layers may be overlapped.

  Through Hole: This type of hole runs through the entire circuit board and can be used for internal interconnection or as a mounting hole for components. Because the through hole is easier to realize in the process and the cost is lower, the through hole is generally used in the printed circuit board. The classification of vias is shown in Figure 2.

  2. Parasitic capacitance of vias

  The via itself has parasitic capacitance to the ground. If the diameter of the isolation hole of the via on the ground layer is D2, the diameter of the via pad is D1, the thickness of the pcb is T, and the dielectric constant of the board substrate is ε, then The magnitude of the parasitic capacitance of the via is approximated by:

  C=1.41εTD1/(D2-D1)

  The main impact of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit. The smaller the capacitance value, the smaller the impact.

  3. Parasitic inductance of vias

  The via itself has parasitic inductance. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the via is often greater than the influence of the parasitic capacitance. The parasitic series inductance of the via will weaken the effect of the bypass capacitor and reduce the filtering effect of the entire power system. If L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center drilled hole, the parasitic inductance of the via is approximately: L=5.08h[ln(4h/d)+1]

  It can be seen from the formula that the diameter of the via hole has little effect on the inductance, while the length of the via hole has the greatest influence on the inductance.

  4. Non-penetrating via technology

  Non-through vias include blind vias and buried vias.

  In the non-through via technology, the application of blind vias and buried vias can greatly reduce the size and quality of PCBs, reduce the number of layers, improve electromagnetic compatibility, increase the characteristics of electronic products, reduce costs, and also make the design work more Simple and fast. In traditional pcb design and processing, through holes bring many problems. First of all, they occupy a large amount of effective space, and secondly, a large number of through holes are densely packed in one place, which also causes huge obstacles to the inner layer routing of multi-layer PCBs. These through holes occupy the space required for routing, and they densely pass through power and ground. The surface of the wire layer will also destroy the impedance characteristics of the power ground wire layer, making the power ground wire layer ineffective. And conventional mechanical drilling will be 20 times the workload of using non-penetrating hole technology.

  In pcb design, although the size of pads and vias has been gradually reduced, if the thickness of the board layer is not proportionally reduced, the aspect ratio of the vias will increase, and the increase in the aspect ratio of the vias will reduce reliability. With the maturity of advanced laser drilling technology and plasma dry etching technology, it is possible to apply non-penetrating small blind holes and small buried holes. If the hole diameter of these non-penetrating holes is 0.3mm, the parasitic parameters brought by them are The original conventional hole is about 1/10, which improves the reliability of the PCB.

  Due to the use of non-through-via technology, there are few large vias on the pcb, which can provide more space for wiring. The remaining space can be used for large area shielding to improve EMI/RFI performance. At the same time, more remaining space can also be used for the inner layer to partially shield the device and key network cables, so that it has the best electrical performance. By using non-through vias, the device pins can be fanned out more easily, making it easy to route high-density pin devices (such as BGA packaged devices), shortening the wiring length, and meeting the timing requirements of high-speed circuits.


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